Dr. Jonathan “Jonny” Pellish is employed at the Goddard Space Flight Center (GSFC) as the National Aeronautics and Space Administration’s Electrical, Electronic, and Electromechanical (EEE) Parts Manager, responsible for workforce stewardship and coordinating Agency-wide discipline technical activities in the EEE parts and radiation effects engineering communities. Currently, Jonny is also the acting program manager for the NASA Electronic Parts and Packaging (NEPP) Program, which is operated by GSFC for the NASA Office of Safety and Mission Assurance. Dr. Pellish received the B.S. degree in physics from Vanderbilt University in 2004, and the M.S. and Ph.D. degrees in electrical engineering from Vanderbilt University in 2006 and 2008. Jonny has authored or co-authored over 60 refereed publications in addition to numerous conference and workshop presentations. He is a member of the American Institute of Aeronautics and Astronautics and the Institute for Electrical and Electronics Engineers.

Riccardo Mariani is widely recognized as an expert in functional safety and integrated circuit reliability. In his current role as chief functional safety technologist at Intel Corporation, he oversees strategies and technologies for IoT applications that require functional safety, high reliability and performance, such as autonomous driving, transportation and industrial systems.

Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors. He has also won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. He holds a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.

DFT expert, inventor and scientist, mentored many leaders of the DFT industry. During his tenure at Mentor he has built a strong international R&D organization (USA, Canada, Germany, India and Poland) with focus on innovative Design for Test technologies and collaboration with leading semiconductor companies. Under his leadership the team has developed a number of revolutionary industry-first, trend-setting Tessent® products: TestKompress®, the first commercial test compression product, TK/LBIST hybrid with VersaPoint™ technology and Cell-Aware Test technology which provides unprecedented test quality in manufacturing and in-system test. These solutions are increasingly important for smaller technology nodes and automotive applications to satisfy functional safety requirements in safety-critical applications. A Lifetime Fellow of the IEEE, he has published more than 240 IEEE research papers and is co-inventor of more than 100 US and a number of corresponding international patents. His papers and patents have over 12,000 citations and won many prestigious awards, including two Donald Pederson awards for best papers published in the IEEE Transactions on CAD, one on logic synthesis and another on test compression. Both are leading solutions in their respective areas and widely used by the industry. In 2003, he was awarded the prestigious title of “Professor of Science” by the President of Poland. In 2009 he received the Stephen Swerling Innovation Award from Mentor Graphics “for his breakthrough innovation, TestKompress, and his many contributions to revitalizing Mentor's DFT business to its current position as #1 test business in EDA”. In 2018, Rajski received the Siemen’s Inventor of the Year 2018 Lifetime Achievement Award for his extensive contributions to DFT.

Dr. Raoul VELAZCO was born in Montevideo (Uruguay) in 1952. Living in France since 1976, he got there the PhD and the Doctor ès Sciences in Computer Sciences in 1982 and 1990 respectively, both from INPG (Institut National Polytechnique de Grenoble). Since 1984 he is a researcher at CNRS (French Research Agency), being presently Director of Researches. Since 1996 he works at TIMA Labs. (Grenoble) where he leads RIS (Reliable Integrated circuits and Systems) research group. His researches concern the methodology to assess the sensitivity to the effects of radiation of integrated circuits and systems, the potential solutions to deal with these effects, the related tests in particle accelerator facilities and experiments at high altitude (mountains, planes, scientific satellites). Dr. Velazco was general chair of two important events related with these topics: IEEE RADECS (RADiation and its Effects in Circuits and Systems) in 2001 and Single Event Effects Symposium in 2009. He was the Technical Chair of RADECS 2012 held September 2012 in Biarritz (France). He is also the creator and general co-chair of the international school SERESSA (School on the Effects of Radiation on Embedded Circuits for Space Applications), whose 2018 edition was held in Noordwijk (The Netherlands) organized in cooperation with European Space Agency (ESA/ESTEC).

Raymond Park is the Manager of DRAM Technical Marketing at SK Hynix. Current efforts include understanding memory requirements for automated vehicles and supporting various automotive processor partners, Tier-1s and OEMs with their system developments.

As the founder of KPM Consulting Klaus created strategies, defined product portfolios, and produced go-to-market plans for major companies in the EU and USA. During his career, he worked for Siemens Components Group, now Infineon, in various marketing and sales positions covering products like MOSFETs, ICs and Memories. He was one of the pioneers in placing MOSFETs successfully in market. In 1994, he joined Siliconix in Europe as head of regional marketing and successfully launched the first trench power MOSFETs into the market. In 2000, he moved to the US where he spearheaded Vishay’s market development, generating an average growth rate of 38% per year. In 2006, he was promoted to division head for their automotive business with full P&L responsibility. Under his tenure, Vishay grew into the top 3 power MOSFET suppliers in the automotive world. In 2011, he joined Power Integrations, driving the automotive and industrial marketing with a special focus on new power technologies. In 2016, he joined Amkor Technology where he was responsible for Automotive Marketing. There he led the integration of J-Devices automotive business into Amkor, implementing automotive standards in all 11 lines and drove the automotive revenue over $1 billion. As Director, Group Technology Strategy, Klaus J. Pietrczak was responsible for leading the JCET Group’s marketing and business development activities in the automotive, wirebond and memory markets. Klaus received a Dipl. Ing. (MSEE) from Fachhochschule Wiesbaden, Germany.

Sung Chung has been CTO at QRT Inc. Korea since May 2017 with responsibility of leading R&D team; developing new market segment through technical marketing and creating new solutions for ISO 26262 Automotive Functional Safety Standard. Mr. Sung joined the company after spending 35+ years in Silicon Valley. Before joining QRT Inc. Korea, Chung served various positions at Cisco System where he spent 14+ years. During his stay at Cisco Systems, Chung developed companywide SEU mitigation process, had responsibility of managing ASIC DFT groups and developing various DFT techniques, where he developed AC JTAG, and it became a IEEE Std. 1149.6-2003 - IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks. Chung also participated various IEEE Test and JEDEC SEU Standard activities as a working group member. Mr. Chung received a Master of Science Degree in EE from Florida Institute of Technology, Melbourne FL, USA. He published over 40+ technical papers/presentations on DFT, Boundary-Scan, BIST, and SEU. He holds 20 US and Korean Patent in the field of test and DFT. Sung is a Life Member of IEEE. Currently, he lives in Korea and speaks fluent English and Korean.

Dr. Raoul VELAZCO was born in Montevideo (Uruguay) in 1952. Living in France since 1976, he got there the PhD and the Doctor ès Sciences in Computer Sciences in 1982 and 1990 respectively, both from INPG (Institut National Polytechnique de Grenoble). Since 1984 he is a researcher at CNRS (French Research Agency), being presently Director of Researches. Since 1996 he works at TIMA Labs. (Grenoble) where he leads RIS (Reliable Integrated circuits and Systems) research group. His researches concern the methodology to assess the sensitivity to the effects of radiation of integrated circuits and systems, the potential solutions to deal with these effects, the related tests in particle accelerator facilities and experiments at high altitude (mountains, planes, scientific satellites). Dr. Velazco was general chair of two important events related with these topics: IEEE RADECS (RADiation and its Effects in Circuits and Systems) in 2001 and Single Event Effects Symposium in 2009. He was the Technical Chair of RADECS 2012 held September 2012 in Biarritz (France). He is also the creator and general co-chair of the international school SERESSA (School on the Effects of Radiation on Embedded Circuits for Space Applications), whose 2018 edition was held in Noordwijk (The Netherlands) organized in cooperation with European Space Agency (ESA/ESTEC).

Sang Lee is a General Manager of Outermost Technology, a company that provides material analysis, reverse engineering, failure analysis, and reliability test services to Silicon Valley customers. Sang started his career as a materials scientist at Veeco, after which he expanded his expertise to the semiconductor industry while working at Applied Materials and then photovoltaic industry at Solyndra. Recently, he was a General Manager at Intermolecular, leading the development of new customized materials for industries which includes semiconductor, display, LED, energy storage, photovoltaic, and electrochromic windows. His expertise in metrology covers various techniques such as XPS, AES, TEM/EDX/EELS, SEM/EDX, SIMS, XRD/XRF/XRR, SE, and AFM/STM, which are key techniques used in reverse engineering and failure analysis of devices.

Mr. Youngnoh Kim has been leading technical marketing at QRT Inc. Korea since Jan 2014; developing new market segment and creating new solutions for reliability test. Mr. Kim joined the company after spending 4 years in Hewlett-Packard and 15 years in SK Hynix. During his stay at Hewlett-Packard, Youngnoh monitored supplier quality performances and continuous quality improvement activities and made reliability projection based on memory supplier reliability tests and actual field performance. He won 2013 HP President Quality Award by improving field quality of server memory in the course of study in HP Lean Six Sigma Black Belt. He also had responsibility of leading/performing supplier audit for Wafer Fab/Component/Module/SSD in DRAM and NVM. Youngnoh was global engineering and quality account manager in SK Hynix US for 4 years in the biz with Dell so SK Hynix’s share in DRAM biz increased from 10% to over 40% while he was working in US for three years. Dell became number one customer to SK Hynix and SK Hynix became number one DRAM supplier to Dell by qualifying PC memory, server memory and Graphics memory.